The invention relates to complementary-metal-oxide-semiconductor (CMOS) devices that are commonly used in low-power integrated-circuit (IC) devices. Such devices have made possible a host of battery-operated systems such as watches and toys that draw so little current that a small battery will last for an extended period. For example a miniature single-cell battery will power a wristwatch for an entire year. High-energy cells will operate for several years.
While CMOS circuits require very little power, it has been found that certain inherent mechanisms require appreciable power in normal operation. For example, in a CMOS inverter gate the operation is most efficient when the applied voltage is equal to the sum of P and N channel device thresholds. When the supply exceeds this value, excess power is drawn because at its trip point such a gate is conductive. Power also is drawn by the charging and discharging of the output capacitance and is proportional to the frequency of the charge-discharge cycle. As the battery discharges, its voltage will slump with the end of life being a function of the lowest voltage at which the circuit will function. Clearly it is desirable to operate the CMOS circuitry at a battery voltage that is well above sum of thresholds. Thus, with a fresh battery, which has a relatively high voltage, the conventional CMOS circuits will draw an excess current.
In my copending application, Ser. No. 216,232, filed Dec. 15, 1980, and assigned to the assignee of the present invention, a low-power CMOS oscillator is described, in which the P and N-channel transistors are optimally biased for Class B operation. Such an oscillator will start and run at very low supply voltages, is itself very efficient and, as will be shown below, is an excellent source of clocking potentials.